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[Other resource] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。
Platform: | Size: 1740 | Author: 左麟 | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[VHDL-FPGA-Verilog] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152576 | Author: 冯申 | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] fir_finall

Description:
Platform: | Size: 1024 | Author: 刘东 | Hits:

[VHDL-FPGA-Verilog] FIR_filter_DA_machine

Description: 用verilog 代码编写的179阶FIR数字滤波器，采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
Platform: | Size: 1024 | Author: a | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] coeff_rom_2_5

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[Software Engineering] FPGAFIR

Description: FPGA-based high-order FIR filter design
Platform: | Size: 4537344 | Author: 玉玲 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Communication-Mobile] fir

Description: 用verilog实现fir滤波器,实现了一个8阶的fir滤波器-design the fir filter use verilog lanuage
Platform: | Size: 1024 | Author: 叶敏 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
Platform: | Size: 140288 | Author: yaaaan | Hits:

[VHDL-FPGA-Verilog] 数字信号处理的FPGA实现-第三版-verilog源程序

Description: 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
Platform: | Size: 4568064 | Author: btty | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR filter in verilog for xilinx ise design suit
Platform: | Size: 190464 | Author: addy007 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir滤波器的简单实现，主要用于学习与理解(Simple implementation of the fir filter, mainly for learning and understanding)
Platform: | Size: 1024 | Author: 未曾走远 | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

[hardware design] fir滤波器

Description: FIR滤波器，verilog编写，可以正常使用(FIR filter, written by verilog, can be used normally, very good)
Platform: | Size: 1031168 | Author: happytian | Hits:
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